Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703
authorAndre Przywara <[email protected]>
Mon, 20 May 2019 13:57:06 +0000 (14:57 +0100)
committerAndre Przywara <[email protected]>
Thu, 6 Jun 2019 13:27:37 +0000 (14:27 +0100)
commit5f5d0763875218893d3831a685886c17d20be940
tree777151cf55daa16119f9035dd5b6d9fa1d7730b8
parent49d969bbb3ca7e738bc6ef560e44c0047a9925cc
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703

Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html

Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <[email protected]>
docs/design/cpu-specific-build-macros.rst
include/lib/cpus/aarch64/neoverse_n1.h
lib/cpus/aarch64/neoverse_n1.S
lib/cpus/cpu-ops.mk